The invention relates generally to etching of dielectric layers in an integrated circuit fabrication process, and more particularly to a technique for etching via holes in a dual-layer dielectric for metallization of the circuit.
In conventional integrated circuit fabrication processes, circuit devices such as transistors are formed in a semiconductor substrate. Metal or other conductive contacts and interconnects are formed over and through a dielectric layer, such as a field oxide layer, deposited over the semiconductor substrate. In large-scale (LSI) and very large-scale (VLSI) integrated circuit technologies, it is common to have multiple layers of metallization forming interconnects over the surface of an integrated circuit. An insulative dielectric is deposited between each metallization layer. Electrical contact vias are formed between metallization layers by forming via holes in the dielectric layer in predetermined locations to expose selected areas of the preceding metal layer for contact by deposition of a succeeding metallization layer.
Conventional integrated circuit metallization processes use either silicon oxide or silicon nitride as the interlayer dielectric material. U.S. Pat. No. 4,545,852 commonly assigned herewith, discloses a dual-layer dielectric process. This dual-layer dielectric provides a number of process advantages but one disadvantage is that etching the via holes through two different layers requires two different etches.
The top layer of the dual dielectric film is plasma-enhanced chemical vapor-deposited (PECVD) silicon nitride and the bottom layer is PECVD silicon oxide. Silicon nitride layers are typically etched in a fluorine-rich plasma etch, while silicon oxide layers are typically etched in a fluorine-deficient fluorocarbon plasma etch. Nitride layers are etched more by chemical reactions while oxide etching generally requires ion bombardment. The chemical etching of silicon nitride results in an isotropic profile of the opening etched into the layer. Ion bombardment of a silicon oxide layer results in what is called an anisotropic, straight-walled profile. As heretofore practiced, these two different etch methods have been carried out in discrete processes and separate etching chambers.
To form via holes in a dual-layer dielectric using these etching techniques requires that the nitride layer be etched in a first step in one processing chamber, transferred to a second processing chamber after via holes have been etched through the nitride layer, and etched in a second processing step to extend the via holes through the oxide layer to expose an upper surface of a metal layer beneath the oxide layer. The separate processes thus require more time, equipment, labor and processing complexity than single-dielectric layer metallization processes. There is also a risk of wafer contamination during transfer between processing chambers.
Another problem that arises generally in forming vias is that metal deposition/coverage down into a straight-walled via hole (vertical anisotropic profile) is difficult. Without proper metal coverage, the integrated circuit will not function properly. Preferably, the via hole should have a sloped sidewall, which is difficult to obtain in a dual-layer dielectric composed of a layer of silicon nitride atop a layer of silicon oxide. Isotropic chemical etching of nitride presents a two-fold problem: One is that the thickness of the nitride layer is typically nonuniform, particularly so in multilayer metallizations. As multiple layers are built up, interconnections and crossovers of interconnections in different layers make the surface uneven. This unevenness is replicated in the PECVD oxide and nitride layers. Conventionally, to reduce unevenness so that a succeeding metallization layer can be more reliably deposited, requires an intervening planarization step. In this step, elevated areas of the nitride layer are thinned. If the nitride layer is chemically etched, as is conventional, then where the nitride layer is thin the chemical etch will continue to etch the nitride laterally underneath the resist layer. Consequently, via holes formed where the nitride film is thin will be larger than those formed where the nitride film is thick. This distribution of via hole sizes across a wafer results in process problems, with metal coverage of the large holes being one of those problems. Even a single oxide layer dielectric via etch generally requires two different etches, an isotropic etch followed by an anisotropic etch, in different etching chambers; otherwise, metal coverage problems will occur.
The prior technique of etching via holes in a dual-layer dielectric generally produces via holes with vertical sidewalls through the nitride layer, a stair-step profile in the upper portion of the oxide layer, and a hole of reduced diameter extending through the oxide layer as shown in dashed lines in FIG. 2.
Accordingly, a need remains for a better method of forming via holes in dual-layer dielectric for the formation of vias. R. C. Langley et al. of Micron Technology recently proposed a one-chamber polycide sandwich etching method of forming polycide hybrid gate structures consisting of a metal silicide on top of polysilicon (Semiconductor International, October 1989, pages 95-97). It would be desirable to have a single chamber via etching process that is effective and reliable to form via holes in a dual-layer dielectric.